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2-mbit (128k x 18) flow-through sync sram cy7c1324h cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-00208 rev. *b revised april 26, 2006 features ? 128k x 18 common i/o ? 3.3v core power supply ? 3.3v/2.5v i/o supply ? fast clock-to-output times ? 6.5 ns (133-mhz version) ? provide high-performance 2-1-1-1 access rate ? user-selectable burst counter supporting intel ? pentium ? interleaved or linear burst sequences ? separate processor and controller address strobes ? synchronous self-timed write ? asynchronous output enable ? offered in jedec-standard lead-free 100-pin tqfp package ? ?zz? sleep mode option functional description [1] the cy7c1324h is a 128k x 18 synchronous cache ram designed to interface with high-speed microprocessors with minimum glue logic. maximum access delay from clock rise is 6.5 ns (133-mhz version). a 2-bit on-chip counter captures the first address in a burst and increments the address automati- cally for the rest of the burst access. all synchronous inputs are gated by registers controlle d by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (ce 1 ), depth-expansion chip enables (ce 2 and ce 3 ), burst control inputs (adsc , adsp , and adv ), write enables (bw [a:b] , and bwe ), and global write ( gw ). asynchronous i nputs include the output enable (oe ) and the zz pin . the cy7c1324h allows either interleaved or linear burst sequences, selected by the mode input pin. a high selects an interleaved burst sequence, while a low selects a linear burst sequence. burst accesses can be initiated with the processor address strobe (adsp ) or the cache controller address strobe (adsc ) inputs. address advancement is controlled by the address advancement (adv ) input. addresses and chip enables are registered at rising edge of clock when either address strobe processor (adsp ) or address strobe controller (adsc ) are active. subsequent burst addresses can be internally generated as controlled by the advance pin (adv ). the cy7c1324h operates from a +3.3v core power supply while all outputs may operate with either a +3.3v or +2.5v supply. all inputs and outputs are jedec-standard jesd8-5-compatible. note: 1. for best-practices recommendations, please refer to the cypress application note system design guidelines on www.cypress.com. address register adv clk burst counter and logic clr q1 q0 adsc ce 1 oe sense amps memory array adsp output buffers input registers mode ce 2 ce 3 gw bwe a 0,a1,a bw b bw a dq b ,dqp b write register dq a ,dqp a write register enable register a[1:0] dqs dqp a dqp b dq b ,dqp b write driver dq a ,dqp a write driver sleep control zz logic block diagram [+] feedback [+] feedback
cy7c1324h document #: 001-00208 rev. *b page 2 of 15 selection guide 133 mhz unit maximum access time 6.5 ns maximum operating current 225 ma maximum standby current 40 ma pin configurations 100-pin tqfp pinout a a a a a 1 a 0 nc/72m nc/36m v ss v dd nc/9m a a a a a nc/4m a nc v ddq v ss nc dqp b dq a dq a v ss v ddq dq a dq a v ss nc v dd dq a dq a v ddq v ss dq a dq a nc nc v ss v ddq nc nc nc nc nc nc v ddq v ss nc nc dq b dq b v ss v ddq dq b dq b nc v dd nc v ss dq b dq b v ddq v ss dq b dq b dqp b nc v ss v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk gw bwe oe adsp a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 byte a a adv adsc zz mode nc/18m nc byte b cy7c1324h [+] feedback [+] feedback
cy7c1324h document #: 001-00208 rev. *b page 3 of 15 pin definitions name i/o description a0, a1, a input- synchronous address inputs used to select one of the 128k address location s. sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are sampled active. a [1:0] feed the 2-bit counter. bw a, bw b input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes are wr itten, regardless of the values on bw [a:b] and bwe ). bwe input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk input-clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. adsp is ignored if ce 1 is high . ce 1 is sampled only when a new external address is loaded. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 2 is sampled only when a new external address is loaded. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/desel ect the device. ce 3 is sampled only when a new external address is loaded. oe input- asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv input- synchronous advance input signal, sampled on the rising edge of clk . when asserted, it automatically increments the address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the de vice are captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high adsc input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the de vice are captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. zz input- asynchronous zz ?sleep? input, active high . when asserted high places the device in a non-time-critical ?sleep? condition with data integrity preserved. fo r normal operation, this pin has to be low or left floating. zz pin has an internal pull-down. dqs dqp a, dqp b i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they de liver the data contained in the memory location specified by the addresses pres ented during the previo us clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dqs and dqp [a:b] are placed in a tri-state condition. v dd power supply power supply inputs to the core of the device . v ss ground ground for the device . v ddq i/o power supply power supply for the i/o circuitry . mode input- static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. this is a strap pin and should remain static during device operation. mode pin has an internal pull-up. nc no connects . not internally connected to the die. 4m, 9m, 18m, 72m, 144m, 288m, 576m, and 1g are address expansion pins and are not internally connected to the die. [+] feedback [+] feedback
cy7c1324h document #: 001-00208 rev. *b page 4 of 15 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t cdv ) is 6.5 ns (133-mhz device). the cy7c1324h supports secondary cache in systems utilizing either a linear or interleaved burst sequence. the interleaved burst order supports pentium and i486? processors. the linear burst sequence is suited for processors that utilize a linear burst s equence. the burst order is user-selectable, and is determined by sampling the mode input. accesses can be initiated with either the processor address strobe (adsp ) or the controller address strobe (adsc ). address advancement th rough the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burst counter captures the firs t address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualif ied with the byte write enable (bwe ) and byte write select (bw [a:b] ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip selects (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state co ntrol. adsp is ignored if ce 1 is high. single read accesses a single read access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , and ce 3 are all asserted active, and (2) adsp or adsc is asserted low (if the access is initiated by adsc , the write inputs must be deasserted during this first cycle). the address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. if the oe input is asserted low, the requested data will be available at the data outputs a maximum to t cdv after clock rise. adsp is ignored if ce 1 is high. single write accesses initiated by adsp this access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , ce 3 are all asserted active, and (2) adsp is asserted low. the addresses presented are loaded into the address register and the burst inputs (gw , bwe , and bw [a:b] ) are ignored during this first clock cycle. if the write inputs are asserted active (see write cycle descriptions table for appropriate states that indicate a write) on the next clock rise, the appropriate data will be latched and written into the de vice. byte writes are allowed. during byte writes, bwa controls dqa and bwb controls dqb. all i/os are tri-stated during a byte write. since this is a common i/o device, the asynchronous oe input signal must be deasserted and the i/os must be tri-stated prior to the presentation of data to dqs. as a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of oe . single write accesses initiated by adsc this write access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , and ce 3 are all asserted active, (2) adsc is asserted low, (3) adsp is deasserted high, and (4) the write input signals (gw , bwe , and bw [a:b]) indicate a write access. adsc is ignored if adsp is active low. the addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. the information presented to dq[a:d] will be written into the specified addr ess location. byte writes are allowed. during byte writes, bwa controls dqa and bwb controls dqb. all i/os are tri-st ated when a write is detected, even a byte write. since this is a common i/o device, the asynchronous oe input signal must be deasserted and the i/os must be tri-stated prior to the presentation of data to dqs. as a safety precaution, the data lines are tri-stated once a write cycle is detec ted, regardless of the state of oe . burst sequences the cy7c1324h provides an on-chip two-bit wraparound burst counter inside the sram. the burst counter is fed by a [1:0] , and can follow either a linear or interleaved burst order. the burst order is determined by the state of the mode input. a low on mode will select a linear burst sequence. a high on mode will select an interleaved burst order. leaving mode unconnected will cause th e device to default to an interleaved burst sequence. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ces, adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1, a0 second address a1, a0 third address a1, a0 fourth address a1, a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a 1 , a 0 second address a 1 , a 0 third address a 1 , a 0 fourth address a 1 , a 0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 [+] feedback [+] feedback
cy7c1324h document #: 001-00208 rev. *b page 5 of 15 zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz sleep mode standby current zz > v dd ? 0.2v 40 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to sleep current t his parameter is sampled 2t cyc ns t rzzi zz inactive to exit sleep curr ent this parameter is sampled 0 ns truth table [2, 3, 4, 5] cycle description address used ce 1 ce 2 ce 3 zz adsp adsc adv we oe clk dq deselected cycle, power-down none h x x l x l x x x l-h tri-state deselected cycle, power-down none l l x l l x x x x l-h tri-state deselected cycle, power-down none l x h l l x x x x l-h tri-state deselected cycle, power-down none l l x l h l x x x l-h tri-state deselected cycle, power-down none x x x l h l x x x l-h tri-state sleep mode, power-down none x x x h x x x x x x tri-state read cycle, begin burst external l h l l l x x x l l-h q read cycle, begin burst external l h l l l x x x h l-h tri-state write cycle, begin burst external l h l l h l x l x l-h d read cycle, begin burst external l h l l h l x h l l-h q read cycle, begin burst external l h l l h l x h h l-h tri-state read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h tri-state read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h tri-state write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h tri-state read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h tri-state write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d notes: 2. x = ?don't care.? h = logic high, l =logic low. 3. write = l when any one or more byte write enable signals (bw a , bw b ) and bwe = l or gw = l. write = h when all byte write enable signals (bw a , bw b ), bwe , gw = h.the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 4. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw [a: b] . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the outputs to tri-state. oe is a don't care for the remainder of the write cycle 5. oe is asynchronous and is not sampled with t he clock rise. it is masked internally during write cycles. during a read cycle all d ata bits are tri-state when oe is inactive or when the device is deselected , and all data bits behave as output when oe is active (low) [+] feedback [+] feedback
cy7c1324h document #: 001-00208 rev. *b page 6 of 15 truth table for read/write [2, 3] function gw bwe bw b bw a read h h x x read h l h h write byte (a, dqp a )hlhl write byte (b, dqp b )hllh write all bytes h l l l write all bytes l x x x [+] feedback [+] feedback
cy7c1324h document #: 001-00208 rev. *b page 7 of 15 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v dd relative to gnd........ ?0.5v to +4.6v supply voltage on v ddq relative to gnd ...... ?0.5v to +v dd dc voltage applied to outputs in tri-state........................................... ?0.5v to v ddq + 0.5v dc input voltage ................................... ?0.5v to v dd + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0c to +70c 3.3v ? 5%/+10% 2.5v ?5% to v dd industrial ?40c to +85c electrical characteristics over the operating range [6, 7] parameter description test conditions min. max. unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage for 3.3v i/o 3.135 v dd v for 2.5v i/o 2.375 2.625 v v oh output high voltage for 3.3v i/o, i oh = ?4.0 ma 2.4 v for 2.5v i/o, i oh = ?1.0 ma 2.0 v ol output low voltage for 3.3v i/o, i ol = 8.0 ma 0.4 v for 2.5v i/o, i ol = 1.0 ma 0.4 v ih input high voltage for 3.3v i/o 2.0 v dd + 0.3v v for 2.5v i/o 1.7 v dd + 0.3v v il input low voltage [6] for 3.3v i/o ?0.3 0.8 v for 2.5v i/o ?0.3 0.7 i x input leakage current except zz and mode gnd v i v ddq ? 55 a input current of mode input = v ss ?30 a input = v dd 5 a input current of zz input = v ss ?5 a input = v dd 30 a i oz output leakage current gnd v i v ddq , output disabled ?5 5 a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 7.5-ns cycle, 133 mhz 225 ma i sb1 automatic ce power-down current?ttl inputs max. v dd , device deselected, v in v ih or v in v il , f = f max, inputs switching 7.5-ns cycle, 133 mhz 90 ma i sb2 automatic ce power-down current?cmos inputs max. v dd , device deselected, v in v dd ? 0.3v or v in 0.3v, f = 0, inputs static 7.5-ns cycle, 133 mhz 40 ma i sb3 automatic ce power-down current?cmos inputs max. v dd , device deselected, v in v ddq ? 0.3v or v in 0.3v, f = f max , inputs switching 7.5-ns cycle, 133 mhz 75 ma i sb4 automatic ce power-down current?ttl inputs max. v dd , device deselected, v in v dd ? 0.3v or v in 0.3v, f = 0, inputs static 7.5-ns cycle, 133 mhz 45 ma notes: 6. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2), undershoot: v il (ac) > ?2v (pulse width less than t cyc /2). 7. t power-up : assumes a linear ramp from 0v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd . [+] feedback [+] feedback
cy7c1324h document #: 001-00208 rev. *b page 8 of 15 capacitance [8] parameter description test conditions 100 tqfp max. unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3v. v ddq = 2.5v 5pf c clk clock input capacitance 5 pf c i/o input/output capacitance 5 pf thermal resistance [8] parameter description test conditions 100 tqfp package unit ja thermal resistance (junction to ambient) test conditions follow sta ndard test methods and proce- dures for measuring thermal impedance, per eia/jesd51 30.32 c/w jc thermal resistance (junction to case) 6.85 c/w ac test loads and waveforms notes: 8. tested initially and after any design or proc ess change that may affect these parameters. output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.5v 3.3v all input pulses v dd gnd 90% 10% 90% 10% 1 ns 1 ns (c) 3.3v i/o test load output r = 1667 ? r =1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) 2.5v i/o test load [+] feedback [+] feedback
cy7c1324h document #: 001-00208 rev. *b page 9 of 15 switching characteristics over the operating range [9, 10] parameter description -133 unit min. max. t power v dd (typical) to the first access [11] 1ms clock t cyc clock cycle time 7.5 ns t ch clock high 2.5 ns t cl clock low 2.5 ns output times t cdv data output valid after clk rise 6.5 ns t doh data output hold after clk rise 2.0 ns t clz clock to low-z [12, 13, 14] 0ns t chz clock to high-z [12, 13, 14] 3.5 ns t oev oe low to output valid 3.5 ns t oelz oe low to output low-z [12, 13, 14] 0ns t oehz oe high to output high-z [12, 13, 14] 3.5 ns set-up times t as address set-up before clk rise 1.5 ns t ads adsp , adsc set-up before clk rise 1.5 ns t advs adv set-up before clk rise 1.5 ns t wes gw , bwe , bw [a:b] set-up before clk rise 1.5 ns t ds data input set-up before clk rise 1.5 ns t ces chip enable set-up 1.5 ns hold times t ah address hold after clk rise 0.5 ns t adh adsp , adsc hold after clk rise 0.5 ns t weh gw , bwe , bw [a:b] hold after clk rise 0.5 ns t advh adv hold after clk rise 0.5 ns t dh data input hold after clk rise 0.5 ns t ceh chip enable hold after clk rise 0.5 ns notes: 9. timing reference level is 1.5v when v ddq = 3.3v and 1.25v when v ddq = 2.5v 10. test conditions shown in (a) of ac test loads unless otherwise noted. 11. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd (minimum) initially before a read or write operation can be initiated. 12. t chz , t clz , t oelz , and t oehz are specified with ac test conditions shown in part (b) of ac test loads. transition is measured 200 mv from steady-state vo ltage. 13. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention betw een srams when sharing the same data bus. these specifications do not imply a bus contention condition, but reflect pa rameters guaranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions. 14. this parameter is sampled and not 100% tested. [+] feedback [+] feedback
cy7c1324h document #: 001-00208 rev. *b page 10 of 15 timing diagrams read cycle timing [15] note: 15. on this diagram, when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. t cyc t cl clk t adh t ads address t ch t ah t as a1 t ceh t ces data out (q) high-z t clz t doh t cdv t oehz t cdv single read burst read t oev t oelz t chz burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a2 + 2) q(a2 + 3) a2 adv suspends burst. deselect cycle don?t care undefined adsp adsc g w, bwe,bw [a:b] ce adv oe [+] feedback [+] feedback
cy7c1324h document #: 001-00208 rev. *b page 11 of 15 write cycle timing [15, 16] note: 16. full width write can be initiated by either gw low; or by gw high, bwe low and bw [a:b] low. timing diagrams (continued) t cyc t cl clk t adh t ads address t ch t ah t as a1 t ceh t ces high-z burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds t weh t wes byte write signals are ignored for first cycle when adsp initiates burst. adsc extends burst. adv suspends burst. don?t care undefined adsp adsc bwe, bw [a:b] gw ce adv oe data in (d) d ata out (q) [+] feedback [+] feedback
cy7c1324h document #: 001-00208 rev. *b page 12 of 15 read/write timing [15, 17, 18] notes: 17. the data bus (q) remains in high-z following a write cycle unless an adsp , adsc , or adv cycle is performed. 18. gw is high. timing diagrams (continued) t cyc t cl clk t adh t ads address t ch t ah t as a2 t ceh t ces single write d(a3) a3 a4 burst read back-to-back reads high-z q(a2) q(a4) q(a4+1) q(a4+2) q(a4+3) t weh t wes t oehz t dh t ds t cdv t oelz a1 a5 a6 d(a5) d(a6) q(a1) back-to-back writes don?t care undefined adsp adsc bwe, bw [a:b] ce adv oe data in (d) data out (q) [+] feedback [+] feedback
cy7c1324h document #: 001-00208 rev. *b page 13 of 15 zz mode timing [19, 20] notes: 19. device must be deselected when entering zz mode. see cycle descr iptions table for all possible signal conditions to deselect the device. 20. dqs are in high-z when exiting zz sleep mode. timing diagrams (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only [+] feedback [+] feedback
cy7c1324h document #: 001-00208 rev. *b page 14 of 15 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. intel and pentium are registered trademarks and i486 is a tr ademark of intel corporation. all product and company names mentioned in this document may be the tr ademarks of their respective holders. ordering information ?not all of the speed, package and temperature ranges are available. please contact your local sales representative or visit www.cypress.com for actual products offered?. speed (mhz) ordering code package diagram package type operating range 133 CY7C1324H-133AXC 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) lead-free commercial cy7c1324h-133axi 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) lead-free industrial package diagram note: 1. jedec std ref ms-026 2. body length dimension does not include mold protrusion/end flash mold protrusion/end flash shall not exceed 0.0098 in (0.25 mm) per side 3. dimensions in millimeters body length dimensions are max plastic body size including mold mismatch 0.300.08 0.65 20.000.10 22.000.20 1.400.05 121 1.60 max. 0.05 min. 0.600.15 0 min. 0.25 0-7 (8x) stand-off r 0.08 min. typ. 0.20 max. 0.15 max. 0.20 max. r 0.08 min. 0.20 max. 14.000.10 16.000.20 0.10 see detail a detail a 1 100 30 31 50 51 80 81 gauge plane 1.00 ref. 0.20 min. seating plane 100-pin tqfp (14 x 20 x 1.4 mm) (51-85050) 51-85050-*b [+] feedback [+] feedback
cy7c1324h document #: 001-00208 rev. *b page 15 of 15 document history page document title: cy7c1324h 2-mbit (128k x 18) flow-through sync sram document number: 001-00208 rev. ecn no. issue date orig. of change description of change ** 347377 see ecn pci new data sheet *a 428408 see ecn nxr converted from preliminary to final. changed address of cypress semicond uctor corporation on page# 1 from ?3901 north first street? to ?198 champion court? removed 100 mhz speed-bin changed three-state to tri-state. modified ?input load? to ?input leak age current except zz and mode? in the electrical characteristics table. modified test condition from v ih < v dd to v ih < v dd replaced package name column with package diagram in the ordering information table. updated the ordering information table. replaced package diagram of 51-85050 from *a to *b *b 459347 see ecn nxr included 2.5v i/o option updated the ordering information table. [+] feedback [+] feedback

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